Complementary to global clocks there are separate clock oscillators dedicated to GTH links and DDR memories. The global clock network is based on LVDS signalling to assure high level of signals integrity and immunity to distractions. The global clock network can be also driven from external sources via dedicated SMA connectors as well as from backplane and daughter card sockets.
![fpga simulation estimate gates fpga simulation estimate gates](https://upload.wikimedia.org/wikipedia/commons/f/fa/Altera_StratixIVGX_FPGA.jpg)
![fpga simulation estimate gates fpga simulation estimate gates](https://www.electronicsforu.com/wp-contents/uploads/2016/06/fig-2-1.jpg)
It also provides multiple configuration options due to integrating different oscillators, programmable clock synthesizers and crosspoint switch multiplexers. Very precisely designed clocking block provides 5 length aligned global clock lines routed to each FPGA device. Highest I/O count packages of UltraScale devices and proper on-board traces routing assure reliable LVDS and GTH transfers up to the device inherent limits. Larger capacity of 316 Million gates can be achieved with four HES-US-1320 boards connected in the backplane board HES7BPX4. Each UltraScale FPGA module is connected with DDR4 SO-DIMM to support up to 48 GB aggregated memory. The board provides estimated capacity of 79 Million gates and is easily extendable via backplane and daughter card non-proprietary connectors (BPX & FMC).
![fpga simulation estimate gates fpga simulation estimate gates](https://images.slideplayer.com/25/7810425/slides/slide_3.jpg)
HES-US-1320 Prototyping and Emulation Main BoardĪldec’s large capacity board with three XCVU440 logic modules is targeted to high speed physical prototyping and emulation of ASIC and SoC designs.